`timescale 1ns / 1ns // 1ns -> 0.01ms
module test_display();
// 输入
reg clk;
reg rst_n;
reg [31:0] display;
reg  display_vld;	
// 输出
wire  [7:0]  seg_sel;
wire  [7:0]  segment;
// 例化
segment_prj a(
    .rst_n(rst_n),
    .clk(clk),
    .display(display),
    .display_vld(display_vld),
    .seg_sel(seg_sel),
    .segment(segment)  
);
always #5 clk = ~clk;
initial begin
	// 初始化输入信号
	clk = 1'b0;
	rst_n = 1'b1;
	display = 32'b0000_0000_0000_0000_0000_0011_1001_0010;
	display_vld = 1;
	#20
	rst_n = 1'b0;
end

endmodule
